module Comp (

    // Input 
	input signed [31:0] a,
	input signed [31:0] b,
	input [2:0] op,

	// Output
	output [0:0] compout

    );

    reg [0:0] result;
    assign compout = result;

    always @(a or b or op) begin

        // Operation code -- decides which operation shall be executed
        case (op)
    
            3'b000: begin
                result <= (a == b);
            end

            3'b001: begin
                result <= (a[31] ^ b[31]) ? (a <= b) : (a >= b);
            end

            3'b010: begin
                result <= (a[31] ^ b[31]) ? (a >= b) : (a <= b);
            end

            3'b011: begin
                result <= (a[31] ^ b[31]) ? (a < b) : (a > b);
            end

            3'b100: begin
                result <= (a[31] ^ b[31]) ? (a > b) : (a < b);
            end

            3'b101: begin
                result <= (a != b);
            end

            default: begin
                result <= 1'bx;
            end
    
        endcase

    end

endmodule
